Amplifier having a high power source noise repression ratio

ABSTRACT

An amplifier comprising a pair of differential input MISFETs, a current mirror circuit connected between the drains of the differential input MISFETs and a power source terminal, a phase compensation circuit connected to the drain of one of the differential input MISFETs, an output stage amplification circuit amplifying the signal produced at the drain of one of the differential input MISFETs, a phase regulation circuit such as a capacitor connected to the other of the differential input transistors, and a feedback circuit feeding back the output signal produced from the output stage amplification circuit to the other of the differential input MISFETs in order to apply negative feedback to the amplifier. Since the capacitor is provided, the phase of the power source noise can be made substantially equal to the phase of noise occurring at the drain of one of the differential input MISFETs due to the power source noise. Hence, hardly any noise is produced from the output stage amplification circuit. Since feedback is applied to the amplifier, the noise occurring at the drain of the other of the differential input MISFETs operates in such a manner as to limit the amount of change of the drain voltage of one of the differential input MISFETs due to the noise. As a result, a large change of the output signal due to the power source noise can be prevented. Furthermore, since an element to be added for this purpose may be merely a capacitor, a significant increase in the number of circuit elements can be avoided.

BACKGROUND OF THE INVENTION

This invention relates generally to an amplifier and more particularly,to an operational amplifier suitable for use in an MIS integratedcircuit constituted of MISFETs (insulated gate field effecttransistors).

An amplifier having the circuit construction shown in FIG. 1 has beenknown in the past. In the drawing, reference numeral 1 denotes adifferential input stage, 2 is an output amplification stage and 3 is aphase compensation circuit.

The differential input stage 1 consists of a pair of differential inputMISFETs Q₃ and Q₄, load MISFETs Q₁ and Q₂ that are interposed betweenthe drains of these MISFETs Q₃, Q₄ and a power source line DL and form acurrent mirror circuit, and a constant current MISFET Q₅ interposedbetween the common source of the differential input MISFETs Q₃ and Q₄and the reference potential line SL of the circuit.

The output amplification stage 2 consists of an MISFET Q₆ interposedbetween the power source line DL and an output terminal V_(out) and aconstant current MISFET Q₇ interposed between the output terminalV_(out) and the reference potential line SL of the circuit.

The phase compensation circuit 3 consists of a resistor R₁ and acapacitor C₅ that are connected in series between the output terminalV_(out) and the drain of MISFET Q₂ described above.

A reference voltage V_(ref1) is applied to the gates of MISFETs Q₅ andQ₇ so that these transistors Q₅ and Q₇ operate as constant currentsources.

MISFETs Q₁, Q₂ and Q₆ are p-channel MISFETs while MISFETs Q₃, Q₄, Q₅ andQ₇ are n-channel MISFETs.

The amplifier described above can constitute a voltage follower byconnecting its inversion input terminal IN₁ to its output terminalV_(out) so as to have its non-inversion input terminal IN₂ function asthe input terminal.

If this input terminal IN₂ is connected to a ground potential point, thevoltage follower is believed to be substantially insensitive to thepower source noise. In other words, when the potential of the powersource line DL moves up and down due to the power source noise, thepotential at a node n₁ and the source potential of MISFET Q₆ also moveup and down in response to the former. Accordingly, transient noiseappears at the output terminal V_(out). Since the output terminalV_(out) is connected to the inversion input terminal IN₁, that is, sincefeedback is applied, however, it is generally believed that virtually nonoise appears at the output terminal V_(out).

As a result of examination of the voltage follower composed of theamplifier described above, however, the inventors of the presentinvention have found that noise does appear at the output terminalV_(out) when noise of a relatively high frequency is applied to thepower source voltage.

In other words, since the phase compensation circuit 3 or the like isdisposed at the drain of MISFET Q₂, the value of capacitance coupled tothis transistor Q₂ and the value of capacitance coupled to the drain ofMISFET Q₁ do not balance with each other, so that a phase differenceoccurs between the noise appearing at the drain of MISFET Q₂ and thenoise appearing at the drain of MISFET Q₁.

In the case of noise of a low frequency, the potential differencebetween the drain of MISFET Q₁ and that of MISFET Q₂ that occurs due tothis phase difference is relatively small. For this reason, the drainvoltage of MISFET Q₁ is substantially changed in such a direction as torestrict the potential change of the output terminal V_(out) by feedbackand hence, the potential change of the output terminal V_(out) is smallin the case of power source noise of a low frequency.

In contrast, in the case of a power source noise of a relatively highfrequency, e.g., around 300 KHz, the potential difference between thedrain of MISFET Q₁ and that of MISFET Q₂ occurring due to the phasedifference is relatively great, so that the drain voltage of MISFET Q₁is changed in such a direction as to enlarge the potential change of theoutput terminal V_(out) by applying feedback. Moreover, the capacitor C₅forming the phase compensation circuit cannot cut the power source noiseof a relatively high frequency but transmits it as such to the outputterminal V_(out). For these reasons, the potential change at the outputterminal V_(out) reaches a level that cannot be substantially neglected,in the case of power source noise of a relatively high frequency.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide anamplifier having a high power source noise repression ratio.

It is another object of the present invention to provide an amplifiersuitable for integrated circuit configuration.

Other objects of the present invention will become more apparent fromthe following description to be taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram of a prior art amplifier;

FIG. 2 is a circuit diagram of the amplifier in accordance with oneembodiment of the present invention;

FIG. 3 is a circuit diagram of an experimental circuit to examine thecharacteristics of the amplifier;

FIG. 4 is a characteristic diagram of the amplifier;

FIG. 5 is a sectional view of an MIS integrated circuit; and

FIG. 6 shows a feedback resistor arrangement for use with the amplifierof FIG. 2.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 2 shows an embodiment of the amplifier to which the presentinvention is applied.

The amplifier of this embodiment includes a differential input stage 1,an output amplification stage 2, a phase compensation circuit 3 and biascircuit 4.

In the diagram, each circuit encompassed by dot-and-chain line is formedon one semiconductor substrate by complementary MOS integrated circuittechniques.

The differential input stage 1 consists of a pair of differential inputMISFETs Q₁₉ and Q₂₁, MISFET Q₁₈ having its source connected to the drainof MISFET Q₁₉, though the connection is not particularly limitative,load MISFETs Q₁₇ and Q₂₀ interposed between the drains of MISFETs Q₁₈and Q₂₁ and a power source line DL and forming a current mirror circuit,a constant current MISFET Q₂₂ interposed between the common source ofthe differential input MISFETs Q₁₉ and Q₂₁ described above and areference potential line SL and a capacitor C₁ interposed between thedrain of the load MISFET Q₁₇ and a ground potential point.

The input MISFETs Q₁₉ and Q₂₁ and MISFET Q₁₈ are of an n-channel typewhile the load MISFETs Q₁₇ and Q₂₀ are of a p-channel type, and theconstant current MISFET Q₂₂ is of the n-channel type, although theseconductivity types are not particularly limitative.

The input MISFETs Q₁₉ and Q₂₁ have the same size and the samecharacteristics. Similarly, the load MISFETs Q₁₇ and Q₂₀ forming thecurrent mirror circuit have the same size and the same characteristics.Thus, the offset voltage and drift current of the differential inputstage 1 are reduced to minimum.

In the drawing, the substrate gates of the n-channel MISFETs Q₁₀, Q₁₂,Q₁₈, Q₁₉ and Q₂₁ are respectively connected to their sources asrepresented by dash line while the substrate gates of the othern-channel MISFETs are connected to the lowest potential point, that is,the reference potential line SL. The substrate gates of the p-channelMISFETs are connected to the highest potential point, that is, the powersource line DL.

Since the potential of the substrate gate of each differential inputMISFET is equal to its source potential, the transistor is notsubstantially affected by the characteristic change due to the knownsubstrate effect. As a result, the limit to the input voltage range canbe reduced.

The output amplification stage 2 consists of a p-channel MISFET Q₂₄interposed between the output terminal V_(out) and the power source lineDL and a constant current MISFET Q₂₅ interposed between the drain of thep-channel MISFET Q₂₄ and the reference potential line SL.

The phase compensation circuit 3 consists of a p-channel MISFET Q₂₃ anda phase-compensating capacitor C₂ interposed in series between the drainof MISFET Q₂₁ described above and the output terminal V_(out).

The bias circuit 4 consists of n-channel MISFETs Q₁₀, Q₁₂, Q₁₃ and Q₁₆and p-channel MISFETs Q₈, Q₉, Q₁₁, Q₁₄ and Q₁₅.

The MISFET Q₁₃ forms a current mirror circuit in cooperation with theconstant current MISFET Q₂₂ in the differential input stage 1, with theconstant current MISFETs Q₂₅ in the output amplification stage 2 andwith MISFET Q₁₆, and applies bias to these transistors.

The MISFET Q₈ forms a current mirror circuit in cooperation with MISFETsQ₉ and Q₁₁ and applies bias to them. A predetermined reference voltageV_(ref2) is applied to the gate of MISFET Q₁₀ to keep suitableconductance. Accordingly, the voltage across the power source terminalV_(DD) and the ground terminal GND is divided at the conductance ratiobetween the conductance of MISFET Q₈ and that of MISFET Q₁₀ and theconstant voltage obtained by this voltage division is applied to each ofMISFETs Q₉ and Q₁₁.

In consequence, the MISFET Q₉ is provided with suitable conductance. Thevoltage across the power source terminals V_(DD) and V_(ss) is dividedat the conductance ratio between the conductance of this MISFET Q₉ andthat of MISFET Q₁₃ and the resulting constant voltage is applied to eachof the constant current MISFET Q₂₂ in the differential input stage 1,the constant current MISFET Q₂₅ in the output amplification stage 2 andto MISFET Q₁₆. As a result, MISFETs Q₁₆, Q₂₂ and Q₂₅ operate as theconstant current sources.

The gate of each MISFET Q₁₄ and Q₁₅ is connected to its drain so as toform a kind of diode. Since MISFET Q₁₆ operates as the constant currentsource, the potential at a node n₅ is at a predetermined constant value.Since a predetermined potential is thus applied to MISFET Q₂₃ formingthe phase compensation circuit 3, it operates as a kind of resistanceelement.

In this embodiment, the threshold voltages and characteristics ofMISFETs Q₁₄ and Q₂₀ are set so that the potential at the node n₇ issubstantially equal to that at the node n₂. The threshold voltage andcharacteristics of MISFET Q₁₅ are set so as to form a voltage, betweenthe nodes n₇ and n₅, which corresponds to the voltage to be appliedacross the source and gate of MISFET Q₂₃ so that this transistor has apredetermined resistance value.

Accordingly, even when the potential of the power source voltage line DLchanges, the resistance value of MISFET Q₂₃ can be held at apredetermined value. In other words, when the potential of the powersource line DL changes, the potential of the node n₂, that is, thesource potential of MISFET Q₂₃, changes in response to the former. Inthis case, the potential of each node n₇ and n₅ also changes in responseto the potential change of the power source line DL. Since the potentialchanges of the nodes n₂ and n₅ are equal to each other, the voltageacross the source and gate of MISFET Q₂₃ remains constant without beingsubstantially affected by the potential change of the power source lineDL. Thus, phase compensation can be made stably.

The drain of MISFET Q₁₂ is connected to the gate and the transistoroperates a kind of diode. The potential of the node n₄ is substantiallyconstant because MISFET Q₁₁ operates as a constant current source.

In this embodiment, the MISFET Q₁₈ is operated in the saturation range.The threshold values and characteristics of the constant current MISFETQ₁₁ and diode-connected MISFET Q₁₂ for forming the voltage to be appliedto the gate of Q₁₈ are set so that MISFET Q₁₈ operates in the saturationrange.

Since MISFET Q₁₈ is thus operated in the saturation range, the drainvoltage of the differential input MISFET Q₁₉ can be kept substantiallyconstant even when the potential of the power source voltage line DLchanges due to noise or the like. In other words, the bias to thedifferential input MISFET Q₁₉ is hardly affected by the potential changeof the power source voltage line DL.

This arrangement makes it possible to reduce the transmission of thepower source noise from the input terminal IN₁ to the output terminalV_(out) through a feedback circuit even if such a feedback circuit isdisposed between the input terminal IN₁ and the output terminal V_(out).

Unless MISFET Q₁₈ is disposed, the drain voltage of the differentialinput MISFET Q₁₉ will change in response to the potential change of thepower source voltage line DL. As is well known, MISFETs have parasiticcapacitance due to the overlap of their gate electrodes with the drainregion. Accordingly, the fluctuation of the drain voltage of thedifferential input MISFET Q₁₉ is transmitted to its gate electrode andthen to the output terminal V_(out) through the feedback circuit. If theMISFET Q₁₈ which operates in the saturation range is disposed betweenthe differential input MISFET Q₁₉ and its load circuit as is in thepresent embodiment, the drain voltage of the differential input MISFETcan be kept substantially constant with respect to the potential changeof the power source voltage line DL. As a result, it becomes possible toreduce the transmission of the power source noise from the inputterminal to the output terminal through the feedback circuit.

In the embodiment, a capacitor C₁ is connected to the drain of the loadMISFET Q₁₇ forming the current mirror circuit.

This capacitor C₁ has a capacitance such that the phase of the noiseoccurring at the node n₂ due to the power source noise becomessubstantially equal to the phase of the noise occurring in the powersource line DL due to the power source noise.

The inventors of the present invention examined the relation between thecapacitance of the capacitor C₁ and the power source noise repressionratio (hereinafter referred to as "PSRR") using the experimental circuitillustrated in FIG. 3 and obtained effective PSRR in a range in whichthe capacitance of the capacitor C₁ was substantially equal to that ofthe capacitor C₂ described above. Here, PSRR represents the ratio of theamplitude V_(IN) applied to the power source voltage to the changequantity ΔV_(out) of the output voltage V_(out) thereby generated, asexpressed by the following equation:

    PSRR=20 log (V.sub.IN /ΔV.sub.out)(dB)

As can be seen clearly from this equation, the greater the PSRR, themore insensitive the amplification circuit becomes to the power sourcenoise.

Next, the circuit tested by the inventors of the present invention andthe test results will be described.

FIG. 3 is a circuit diagram of the experimental circuit and FIG. 4 showsthe test results.

The experimental circuit is formed in view of the possibility that theamplification circuit shown in FIG. 2 is used in a switched capacitor.In other words, the experimental circuit consists of an amplificationcircuit OP₁ which is analogous to the amplifier shown in FIG. 2, afeedback capacitor C_(F) connected between the inversion input terminal(-) and the output terminal, a load capacitor C₃, MISFETs Q₂₆ and Q₂₇for simulating a switch in a switched capacitor and a capacitor C₄ forsimulating a capacitor to which a charge is transferred in the switchedcapacitor. The ground potential is applied to the non-inversion inputterminal of the amplification circuit OP₁, one of the electrodes of thecapacitor C₃ and one of the electrodes of the capacitor C₄, and astabilized voltage V_(ss) is applied to the reference potential line SLof the amplification circuit OP₁ and to the gate of the p-channel MISFETQ₂₇. A stabilized voltage V_(DD) is applied to the gate of the n-channelMISFET Q₂₆. The voltage V_(DD) is also applied to the power sourcevoltage line DL of the amplification circuit OP₁ through a signalgeneration circuit which generates noise. This signal generation circuitgenerates a sine wave of 300 KHz having a peak-to-peak amplitude of ±100(mV). Accordingly, a voltage V_(DD) to which 300 KHz noise with apeak-to-peak amplitude of ±100 (mV) is added to applied to the powersource voltage line DL.

In this experimental circuit, the capacitance of the capacitor C₃ is setto 2 (pF) and that of the capacitor C₄, to 20 (pF). Thephase-compensating capacitor C₂ (see FIG. 2) of the amplificationcircuit OP₁ is set to 5 (pF).

The threshold values of the N-channel MISFET and p-channel MISFETforming the experimental circuit are 0.75 (V) and -0.56 (V),respectively. The voltage V_(DD) is 5 (V) with the voltage V_(ss) being-5 (V). The reference voltage V_(ref2) in the amplification circuit OP₁is 2.5 (V), the experimental temperature is 27° C., and the capacitanceof the feedback capacitor C_(F) is 4 (pF). In FIG. 4, the PSRR valuewhen the capacitance of the capacitor C₁ is changed from 4 (pF) to 7(pF) is shown as PS21, and as PS22 when the capacitance of the feedbackcapacitor C_(F) is 30 (pF). Table 2 illustrates the size W/L (W: channelwidth, L: channel length) and conductance of each MISFET forming theamplification circuit OP₁ in the two kinds of experiments describedabove (see FIG. 2).

The characteristic curves PS11, PS12, PS31 and PS32 represent theexperimental results when the threshold voltage V_(thn) of the n-channelMISFET, the threshold voltage V_(thp) of the p-channel MISFET, thecapacitance of the feedback capacitor C_(F), the measuring temperatureand the voltages V_(DD) and V_(ss) are set to those shown in Table 1,respectively.

Judging from the experimental results shown in FIG. 4, the PSRR valuebecomes higher if the capacitance of the capacitor C₁ is a littlegreater than the capacitance of the phase-compensating capacitor C₂ inthe amplifier, e.g., about 5.5 (pF). In other words, the amplifierbecomes more insensitive to the power source noise.

Since the capacitance of the capacitor C₁ is set to a relatively highvalue substantially equal to that of the phase-compensating capacitor C₂as described above, the parasitic capacitance that is unavoidablygenerated when MISFETs Q₁₇, Q₁₈ and the like are formed cannot be usedas the capacitor C₁. In this embodiment, therefore, the capacitor C₁ isdisposed separately from the parasitic capacitance. An example of thestructure of this capacitor C₁ will be described in further detail withreference to FIG. 5.

                                      TABLE 1                                     __________________________________________________________________________                Capacitance   Power Reference                                     Charac-                                                                           Threshold                                                                             of feedback                                                                          Measuring                                                                            source                                                                              voltage                                       teristic                                                                          voltage capacitor C.sub.F                                                                    temperature                                                                          voltage                                                                             V.sub.ref 2                                   curve                                                                             (V)     (pF)   (°C.)                                                                         (V)   (V)                                           __________________________________________________________________________    PS11                                                                              V.sub.ThN = +0.90                                                                      6     90     V.sub.DD = 4.5                                      PS12                                                                              V.sub.ThP = -0.71                                                                     30            V.sub.ss = -4.5                                     PS21                                                                              V.sub.ThN = +0.75                                                                      6     27     V.sub.DD = 5                                                                        2.5                                           PS22                                                                              V.sub.ThP = -0.56                                                                     30            V.sub.ss = -5                                       PS31                                                                              V.sub.ThN = +0.60                                                                      6     -20    V.sub.DD = 5.5                                      PS32                                                                              V.sub.ThP = -0.41                                                                     30            V.sub.ss = -5.5                                     __________________________________________________________________________

                  TABLE 2                                                         ______________________________________                                                          Mutual conductance                                                                          Source-drain                                          W/L       g.sub.m       conductance g.sub.sd                          MISFET  (μm)   (μ)        (μ)                                        ______________________________________                                        Q.sub.8 114/8     4.40 × 10.sup.-5                                                                      4.16 × 10.sup.-7                        Q.sub.9 114/8     4.78 × 10.sup.-5                                                                      1.41 × 10.sup.-7                        Q.sub.11                                                                              114/8     4.43 × 10.sup.-5                                                                      3.94 × 10.sup.-7                        Q.sub.14                                                                              96/8      4.05 × 10.sup.-5                                                                      4.23 × 10.sup.-7                        Q.sub.15                                                                              21/10     1.46 × 10.sup.-5                                                                      6.44 × 10.sup.-7                        Q.sub.17                                                                              120/10    3.75 × 10.sup.-5                                                                      2.80 × 10.sup.-7                        Q.sub.20                                                                              120/10    3.77 × 10.sup.-5                                                                      2.68 × 10.sup.-7                        Q.sub.23                                                                              27.5/8    .sup. 1.27 × 10.sup.-12                                                               2.96 × 10.sup.-5                        Q.sub.24                                                                              170/6     1.81 × 10.sup.-4                                                                      2.38 × 10.sup.-6                        Q.sub.10                                                                              10/27     1.04 × 10.sup.-5                                                                      6.86 × 10.sup.-8                        Q.sub.12                                                                              10/70     6.08 ×  10.sup.-6                                                                     2.94 × 10.sup.-8                        Q.sub.13                                                                              120/16    5.49 × 10.sup.-5                                                                      1.27 × 10.sup.-7                        Q.sub.16                                                                              75/12     4.98 × 10.sup.-5                                                                      5.80 × 10.sup.-8                        Q.sub.18                                                                              100/20    4.07 × 10.sup.-5                                                                      8.06 × 10.sup.-8                        Q.sub.19                                                                              300/10    1.05 × 10.sup.-4                                                                      5.85 × 10.sup.-8                        Q.sub.21                                                                              300/10    1.05 × 10.sup.-4                                                                      4.70 × 10.sup.-8                        Q.sub.22                                                                              200/16    9.30 × 10.sup.-5                                                                      1.05 × 10.sup.-7                        Q.sub.25                                                                              150/6     2.87 × 10.sup.-4                                                                      1.25 × 10.sup.-6                        ______________________________________                                    

Referring back again to FIG. 2, description will be made as to why PSRRof the amplifier can be improved by making the phase of the noiseappearing at the node n₂ substantially equal to that of the noiseappearing in the power source line DL.

The amplifier of this embodiment is used while the feedback circuit isinterposed between the output terminal V_(out) and the inversion inputterminal IN₁. As the feedback circuit, a circuit consisting of aresistance element, (e.g. the resistor R shown in FIG. 6, where theamplifier OP₁ corresponds to the amplifier of FIG. 2) a capacitor, awiring or a parallel connection of a capacitor and a switching elementis used. When an integration circuit is to be formed by use of thisamplifier, for example, a capacitor or a parallel circuit of a capacitorand a switching element is used as the feedback circuit as is known wellin the art. When a voltage follower circuit is to be formed by thisamplifier, a wiring is used as the feedback circuit. In these cases, theground potential is generally applied to the non-inversion inputterminal of the amplifier, though such is not particularly limitative.

Unless the capacitor C₁ is disposed, the capacitance value coupled withthe node n₃ becomes smaller than the capacitance value coupled with thenode n₂. When the potential of the power source line DL is raised bynoise of a relatively high frequency, for example, the potential at thenode n₃ rises in response to the rise of the potential and the potentialat the node n₂ then rises. The potential at the node n₆ rises due to thepotential rise of the node n₂ and that of the power source line DL. Thepotential rise of the node n₆ is transmitted to the gate of MISFET Q₁₉through the feedback circuit. Since it is noise of a high frequency, thepotential at the node n₃ drops to a relatively low level in this time.The potential at the node n₃ is further reduced by MISFET Q₁₉.Accordingly, the potential at the node n₃ drops to a low level, wherebyMISFET Q₂₀ substantially the potential at the node n₂. Since the gatepotential of the p-channel MISFET Q₂₄ is greatly raised, the potentialat the node n₆ is remarkably reduced. Since the potential at the outputterminal V_(out) is thus reduced greatly, noise develops.

In contrast, if the capacitor C₁ is disposed as in this embodiment, thepotential at the node n₃ is kept at a relatively high value when thepotential rise at the node n₆ is transmitted to the gate of MISFET Q₁₉through the feedback circuit. For this reason, even when the potentialat the node n₃ is reduced, the potential is at a higher value than whenthe capacitor C₁ is not disposed. In other words, the potential rise atthe node n₂ is limited to a value lower than when the capacitor C₁ isnot disposed, so that it is possible to prevent the potential at theoutput terminal V_(out) from being reduced excessively by MISFET Q₂₄.

In other words, it is possible to minimize the potential change at theoutput terminal and to improve PSRR. Since the amplitude of thepotential at the node n₂ is limited, it also becomes possible tominimize the potential change transmitted to the output terminal V_(out)through the phase compensation circuit.

Though the improvement for noise of a high frequency has now beenexplained, PSRR of the amplifier in situations involving noise in thelow frequency range can also be improved in the case of noise of a lowfrequency because the potential change at the node n₂ is limited.

The foregoing explains the case where the feedback circuit is disposed,but PSRR of the amplifier can be improved also in the case where thefeedback circuit is not disposed, by connecting a capacitor C₁ havingsuch a capacitance that the phase of the noise in the power source lineDL becomes substantially the same as the phase of the noise appearing atthe node n₂, to the node n₃.

Unless such a capacitor C₁ is disposed, when, for example, the potentialof the power source line DL rises due to the power source noise, thepotential at the node n₃ also rises substantially simultaneously. Sincethe phase compensation circuit is connected to the node n₂, however, thepotential at the node n₂ rises later than the potential rise of thepower source line DL. Accordingly, a relatively large voltage is appliedacross the source and gate of the p-channel MISFET Q₂₄. The conductanceof this MISFET Q₂₄ thus becomes relatively great, causing a relativelylarge change of the potential at the node n₆. In other words, noiseappears at the output terminal V_(out).

When the capacitor C₁ is connected to the node n₃, on the other hand,the phase of the noise occurring at the node n₃ is retarded from thenoise in the power source line DL. In other words, since a delay circuitis composed of the conductance of MISFET Q₁₇ and the capacitor C₁, thepotential change at the node n₃ is much more delayed than the potentialchange in the power source line DL. When, for example, the potential inthe power source line DL rises due to the power source noise, thepotential at the node n₃ rises later than the potential rise of thepower source line DL, so that a relatively large voltage is appliedacross the source and gate of the p-channel MISFET Q₂₀, therebyincreasing the conductance of MISFET Q₂₀ and speeding up the potentialrise at the node n₂.

As can be understood from the description above, the phase of thepotential change occurring at the node n₂ can be regulated bycontrolling the capacitance of the capacitor C₁. Accordingly, the phaseof the potential change occurring at the node n₂ can be madesubstantially the same as the phase of the potential change in the powersource line DL by setting the capacitance of the capacitor C₁ to anappropriate value (substantially equal to capacitance of the capacitorC₂ in this embodiment), so that the voltage applied across the sourceand gate of the p-channel MISFET Q₂₄ becomes smaller than when thecapacitor C₁ is not disposed. Hence, the conductance of MISFET Q₂₄becomes smaller than when the capacitor C₁ is not disposed and thepotential change at the node n₆ becomes smaller. In other words, thenoise appearing at the output terminal V_(out) due to the power sourcenoise can be reduced and PSRR of the amplifier can be improved.

The amplifier shown in FIG. 3 can obtain high PSRR such as shown in FIG.4 due to the two reasons described above.

In FIG. 2, SR1 is a switching regulator which forms a positive voltageV_(DD) with respect to the ground potential and SR2 is a switchingregulator which forms a negative voltage V_(ss) with respect to theground potential.

The switching regulator consists of a switching element, a transformerto which an input voltage switched by the switching element is appliedand which forms an output voltage, and a stabilization circuit whichreceives the output voltage generated by the transformer and controlsthe switching element so that its output voltage reaches a predeterminedvalue, though this construction is not particularly limitative.

Upon the switching operation of the switching element, the switchingregulator forms the output voltage. Undesirable noise unavoidably addsto the output voltage generated from the regulator due to the switchingoperation. The operation speed of the switching operation has beenincreased in order to reduce the size and weight of the switchingregulator. This results in the problem that undesirable noise of arelatively high frequency, e.g., about 300 KHz, adds to the outputvoltage generated by the switching regulator.

The characterizing features of a switching regulator such as the compactsize and light weight can be effectively utilized if the switchingregulator is used as the power feed device for the amplifier which ishighly resistive to the power source noise as in this embodiment.

As described above, an amplifier having high PSRR can be obtained by thesimple construction in which only a capacitor is disposed.

FIG. 5 is a sectional view of an MIS integrated circuit incorporatingtherein the amplifier described above.

Next, the structure of each of the above-mentioned capacitors C₁, C₂, aswell as that of a p-channel MISFET and a n-channel MISFET will bedescribed. The load MISFET Q₂₀ and the differential input MISFET Q₂₁will be dealt with as the typical examples of the p- and n-channelMISFETS, respectively.

A polysilicon layer 111 formed on an N-type single crystal siliconsubstrate 100 via a relatively thick oxide film 106 forms one of theelectrodes of the capacitor C₁ and a silicon oxide layer 113 forms thedielectric layer of the capacitor C₁. An aluminum layer 115 formed onthe polysilicon layer 111 via this silicon oxide layer 113 forms theother electrode of the capacitor C₁. Similarly, a polysilicon layer 112formed on the N-type single crystal silicon substrate 100 via therelatively thick oxide film 106 forms one of the electrodes of thecapacitor C₂ and a silicon oxide layer 114 forms the dielectric layer ofthe capacitor C₂. An aluminum layer 120 formed on the polysilicon layer112 via this silicon oxide layer 114 forms the other electrode of thecapacitor C₂.

Since the layers forming the electrodes of each capacitor are separatedfrom each other and from the substrate by the relatively thick siliconoxide film 106, the parasitic capacitance that would be otherwise formedbetween the electrodes and the substrate can be reduced. Accordingly,the capacitor C₁ (C₂) having a desired value can be formed between thenode n₃ (the node n₆) and the ground potential point (the drain ofMISFET Q₂₃) by selecting suitably the areas of the aluminum layer andpolysilicon layer forming the electrode or the thickness of the siliconoxide film forming the dielectric layer.

Though not particularly limitative, the aluminum layer 115 forming theother electrode of the capacitor C₁ is connected to the node n₂ (seeFIG. 2) and the polysilicon layer 111 forming one electrode, to theground potential point. The aluminum layer 120 forming the otherelectrode of the capacitor C₂ is connected to one of the electrodes ofMISFET Q₂₃ and the polysilicon layer 112 forming one electrode of thecapacitor C₂, to the node n₆ (see FIG. 2).

The p-channel MISFET Q₂₀ consists of p-type diffusion regions 103, 104formed on the n-type silicon substrate 100 and the gate electrode 122consisting of the polysilicon layer formed on the substrate 100 via arelatively thin gate oxide layer 105. The n-channel MISFET Q₂₁ consistsof n-type diffusion regions 107, 108 formed in a p-type well region andthe gate electrode 123 consisting of a polysilicon layer formed on thewell region via a gate oxide layer.

Next, the method of fabricating this MIS integrated circuit will beexplained.

(A) p⁻ type well region 101 is first formed on the N⁻ type singlecrystal silicon substrate 100 in a region where the n-channel MISFET Q₂₁is to be formed. A silicon oxide layer and then a silicon nitride layerare formed in the p⁻ type well region 101 and the region where thep-channel MISFET Q₂₀ is to be formed. Boron and phosphorus areselectively diffused, relatively, into the region where this siliconnitride layer is not formed, thereby forming channel stoppers 102 and109. The surface of the silicon substrate is then oxidized selectivelyusing the silicon nitride layer as the mask, thus forming a field oxidelayer 106.

(B) After the silicon oxide layer and the silicon nitride layer areremoved, the surface of the regions where MISFETs Q₂₀ and Q₂₁ are to beformed is oxidized, forming a thin gate oxide layer (silicon oxidelayer) 105.

(C) Polysilicon is deposited by chemical vapor deposition to the entiresurfaces of the field oxide layer 106 and gate oxide layer 105, and isselectively etched by photoetching to form polysilicon layers 122, 123,111 and 112 so as to leave the portions where the gate electrodes 122and 123 and one electrode 111 and 112 of each capacitor C₁ and C₂ are tobe formed. Next, the gate oxide layer exposed by photoetching is removedby etching.

(D) A photoresist mask is formed in the region where the n-channelMISFET is to be formed and diffusion of a p-type impurity is effectedusing boron or the like. Thus, the gate electrodes (polysilicon layers)122 and the polysilicon layers 111 and 112 come to have low resistance.At the same time, boron is doped to the main surface of the siliconsubstrate 100 in self-registration with the gate electrode 122, therebyforming the p⁺ type diffusion regions as the source and drain regions103 and 104.

(E) After the photoresist mask formed at the step (D) is removed,another photoresist mask is formed in the region where the p-channelMISFET Q₂₀ is to be formed, and an n-type impurity such as phosphorus isdiffused. Thus, the gate electrode (polysilicon layer) 123 comes to havelow resistance. At the same time, phosphorus is doped to the mainsurface of the p⁻ type well region 101 by self-registration and n⁺ typediffusion regions as the drain and source regions 107 and 108 areformed.

(F) After the photoresist mask formed at the step (E) is removed, aphospho-silicate glass layer 110 is formed on the entire surface bychemical vapor deposition. This phosphosilicate glass layer on thesurfaces of the polysilicon layers 111 and 112, that form one eachelectrode of the capacitors C₁ and C₂, is removed by photoetching. Thesurfaces of the polysilicon layers 111 and 112 thus exposed are thenoxidized to form silicon oxide layers 113 and 114 as the dielectriclayers of the capacitors C₁ and C₂.

(G) Contact holes are bored on the phosphosilicate glass in the sourceand drain regions 103, 108 and 104, 107 of MISFETs Q₂₀ and Q₂₁ and onthe phospho-silicate glass on the polysilicon layers 111 and 112 of thecapacitors C₁ and C₂. Incidentally, the contact hole formed on thephosphosilicate glass on the polysilicon layers 111 and 112 is not shownin the drawing.

(H) An aluminum layer is deposited on the entire surface by vapordeposition or the like and etching is then effected in a desired shape.Aluminum wiring layers 116, 117, 118 and 119 as well as aluminum layers115 and 120 covering the polysilicon layers 111 and 112 and then formed.

(I) A final passivation layer 121 is formed on the aluminum wiringlayers and aluminum layers to complete the MIS integrated circuit suchas depicted in FIG. 5.

Incidentally, the n-channel MISFET Q₂₁ is formed on the same p-type wellregion as MISFET Q₁₉, MISFET Q₁₀ is formed in the same p-type wellregion as MISFET Q₁₂ and MISFET Q₁₃, in the same p-type well region asMISFETs Q₁₆, Q₂₂ and Q₂₅. The source region of each MISFET iselectrically connected to the p-type well region in which it is formed.This arrangement can reduce the characteristic change due to thesubstrate effect.

The layers 113 and 114 forming the dielectric of the capacitors C₁ andC₂ may be nitrate layers, respectively. In this case, the capacitors C₁and C₂ having high capacitance can be obtained easily because thedielectric constant of nitrite is higher than that of silicon oxide. Inthe embodiment described above, one of the electrodes of each capacitorC₁ and C₂ consists of polysilicon doped with a p-type impurity, but itmay be also composed of polysilicon to which an n-type impurity isdoped.

Though the amplifier that operates on the two kinds of power sourcevoltages V_(DD) and V_(ss) has been described, the embodiment is notlimitative in particular. For instance, the present invention can bealso applied to the amplifier which operates on one kind of power sourcevoltage V_(DD).

The amplifier to which the present invention is applied is used as anoperational amplification circuit forming a CODEC integrated circuit,for example, to improve the power source noise repression ratio of theCODEC integrated circuit as a whole. However, the present invention isnot particularly limited thereto but can be widely applied to thoseamplifiers (operational amplifiers), as means for improving their PSRR.

Depending upon the fabrication condition of an MIS integrated circuit,the phase of the noise at the node n₂ can be made substantially equal tothat of the noise in the power source line even if the capacitance ofthe capacitor C₁ is not substantially equal to that of the phasecompensating capacitor C₂, thereby improving the PSRR of the amplifier.The capacitance of the capacitor C₁ can be varied depending upon theintended PSRR value.

The phase compensation circuit described above is not particularlylimitative, either.

While some preferred embodiments of the present invention have thus beendescribed, it is understood that the same is not limited but issusceptible of numerous changes and modifications as known to thoseskilled in the art without departing from the spirit or scope of thefollowing claims.

What is claimed is:
 1. An amplifier comprising:a non-inverting inputterminal; an inverting input terminal; a first differential input fieldeffect transistor of a first conductivity type, having the gate thereofconnected to said inverting input terminal; a second differential inputfield effect transistor of the first conductivity type, having the gatethereof connected to said non-inverting input terminal; an active loadcircuit having a first terminal to which the drain of said firstdifferential input field effect transistor is connected, a secondterminal to which the drain of said second differential input fieldeffect transistor is connected, a third terminal to which a power sourceterminal is connected, and a control element connected between saidsecond and third terminal and having the conductance thereof controlledin accordance with the potential of said first terminal; a phasecompensation circuit connected to said second terminal of said activeload circuit; a feedback circuit applying an output signal generated onthe basis of a signal occurring at said second terminal of said activeload circuit to said inverting input terminal; and a phase regulationcircuit connected to said first terminal so that the phase of apotential change of a power source voltage applied to said power sourceterminal becomes substantially equal to the phase of a potential changeoccurring at said second terminal of said active load circuit due to thevoltage change of the power source voltage.
 2. The amplifier as definedin claim 1 wherein said active load circuit comprises a current mirrorcircuit and a first constant current circuit connected to the sources ofsaid first and second differential input field effect transistors. 3.The amplifier as defined in claim 1 which further comprises a thirdfield effect transistor which is connected between said first terminalof said active load circuit and the drain of said first differentialinput field effect transistor and is operated in a saturation range. 4.The amplifier as defined in claim 3 wherein said phase regulationcircuit comprises a first capacitor connected between said firstterminal and a predetermined potential terminal.
 5. The amplifier asdefined in claim 4 wherein said active load circuit comprises a currentmirror circuit and a second constant current circuit connected to thesources of said first and second differential input field effecttransistors.
 6. The amplifier as defined in claim 5 wherein said firstcapacitor comprises a first conductivity layer formed on the mainsurface of a semiconductor substrate via a field insulation film, aninsulating layer formed on the surface of said first conductivity layerand a second conductivity layer formed on said first conductive layervia said insulating layer.
 7. The amplifier as defined in claim 5wherein said current mirror circuit comprises a fourth field effecttransistor of a second conductivity type having the source thereofconnected to said third terminal, the drain thereof connected to saidsecond terminal and the gate thereof connected to said first terminal,and a non-linear element connected between said third terminal and saidfirst terminal.
 8. The amplifier as defined in claim 7 wherein saidnon-linear element comprises a fifth field effect transistor of thesecond conductivity type having the source thereof connected to saidthird terminal and the gate and drain thereof connected to said firstterminal.
 9. The amplifier as defined in claim 7 wherein said phasecompensation circuit comprises a first resistance element and a secondcapacitor.
 10. The amplifier as defined in claim 9 which furthercomprises an output terminal receiving an output signal formed on thebasis of a signal occurring at said second terminal of said currentmirror circuit, and in which said phase compensation circuit comprisessaid first resistance element and said second capacitor that areconnected in series between said second terminal and said outputterminal.
 11. The amplifier as defined in claim 10 wherein said firstresistance element is comprised of the main conductor line of a sixthfield effect transistor receiving at the gate thereof a suitablevoltage.
 12. The amplifier as defined in claim 10 which furthercomprises an output circuit receiving a signal generated at said secondterminal of said current mirror circuit and generating said outputsignal on the basis of said signal received.
 13. The amplifier asdefined in claim 12 wherein said output circuit comprises a seventhfield effect transistor of the second conductivity type, having thesource thereof connected to said power source terminal, the drainthereof connected to said output terminal and the gate thereof connectedto said second terminal of said current mirror circuit, and a thirdconstant current circuit connected to said output terminal.
 14. Theamplifier as defined in claim 10 wherein said feedback circuit iscomprised of a second resistance element connected between said outputterminal and said inverting input terminal.
 15. The amplifier as definedin claim 10 wherein said feedback circuit is comprised of a thirdcapacitor connected between said output terminal and said invertinginput terminal.
 16. The amplifier as defined in claim 10 wherein saidfeedback circuit is comprised of a wiring connected to said outputterminal and to said inverting input terminal.
 17. The amplifier asdefined in claim 2 wherein said current mirror circuit further comprisesan eighth field effect transistor of the second conductivity type,having the source thereof connected to said third terminal, the drainthereof connected to said second terminal and the gate thereof connectedto said first terminal, and a non-linear element connected between saidthird and first terminals.
 18. The amplifier as defined in claim 17wherein said non-linear element comprises a ninth field effecttransistor of the second conductivity type, having the source thereofconnected to said third terminal and the gate and drain thereofconnected to said first terminal.
 19. The amplifier as defined in claim18 wherein said phase compensation circuit comprises a fourth capacitorelectrically connected to said second terminal.
 20. The amplifier asdefined in claim 19 which further comprises an output terminal connectedto said second terminal via said fourth capacitor of said phasecompensation circuit, a tenth field effect transistor of the secondconductivity type, having the gate thereof connected to said secondterminal, the source thereof connected to said power source terminal andthe drain thereof connected to said output terminal, and a fourthconstant current circuit connected to said output terminal.
 21. Anamplifier comprising:a first differential input field effect transistorof a first conductivity type; a second differential input field effecttransistor of the first conductivity type; an active load circuit havinga first terminal to which the drain of said first differential inputfield effect transistor is connected, a second terminal to which thedrain of said second differential input field effect transistor isconnected, a third terminal to which a power source terminal isconnected, and a control element which is connected between said secondand third terminals and whose conductance is controlled in accordancewith the potential at said first terminal; a phase compensation circuitconnected to said second terminal of said active load circuit; an outputcircuit having a fourth terminal to which said power source terminal isconnected, and generating an output signal on the basis of the potentialat said second terminal of said active load circuit; and a phaseregulation circuit connected to said first terminal so that the phase ofa potential change of a power source voltage applied to said powersource terminal and the phase of a potential change occurring at saidsecond terminal of said active load circuit due to the potential changeof said power source voltage become substantially equal to each other.22. The amplifier as defined in claim 21 wherein said phase regulationcircuit comprises a first capacitor connected between said firstterminal and a predetermined power source terminal.
 23. The amplifier asdefined in claim 22 wherein said active load circuit comprises a thirdfield effect transistor of a second conductivity type, having the gatethereof connected to said first terminal, the source thereof connectedto said third terminal and the drain thereof connected to said secondterminal, and a load element connected between said first and thirdterminals.
 24. The amplifier as defined in claim 23 wherein said outputcircuit comprises a fourth field effect transistor of the secondconductivity type, having the source thereof connected to said fourthterminal and the gate thereof connected to said second terminal of saidactive load circuit.
 25. The amplifier as defined in claim 24 whereinsaid load element of said active load circuit comprises a fifth fieldeffect transistor of the second conductivity type, having the sourcethereof connected to said third terminal and the gate and drain thereofconnected to said first terminal.
 26. An amplifier as defined in claim9, wherein said first capacitor has a capacitance value substantiallyequal to or greater than a capacitance value of said second capacitor.27. An amplifier as defined in claim 4, wherein said phase compensationcircuit comprises a first resistance element and a second capacitor andwherein said first capacitor has a capacitance value substantially equalto or greater than a capacitance value of said second capacitor.
 28. Anamplifier as defined in claim 26, wherein said first capacitor isdisposed separately of parasitic capacitance generated by transistors ofsaid amplifier.
 29. An amplifier as defined in claim 27, wherein saidfirst capacitor is disposed separately of parasitic capacitancegenerated by transistors of said amplifier.
 30. An amplifier as definedin claim 22, wherein said phase compensation circuit comprises a firstresistance element and a second capacitor and wherein said firstcapacitor has a capacitance value substantially equal to or greater thana capacitance value of said second capacitor.
 31. An amplifier asdefined in claim 30, wherein said first capacitor is disposed separatelyof parasitic capacitance generated by transistors of said amplifier. 32.An amplifier as defined in claim 26, wherein both said first and secondcapacitors are comprised of a first conductivity layer formed on themain surface of a semiconductor substrate via a field insulating film,an insulating layer formed on the surface of said first conductivitylayer and a second conductivity layer formed on said first conductivitylayer via said insulating layer.
 33. An amplifier as defined in claim27, wherein both said first and second capacitors are comprised of afirst conductivity layer formed on the main surface of a semiconductorsubstrate via a field insulating film, an insulating layer formed on thesurface of said first conductivity layer and a second conductivity layerformed on said first conductivity layer via said insulating layer. 34.An amplifier as defined in claim 30, wherein both said first and secondcapacitors are comprised of a first conductivity layer formed on themain surface of a semiconductor substrate via a field insulating film,an insulating layer formed on the surface of said first conductivitylayer and a second conductivity layer formed on said first conductivitylayer via said insulating layer.